The present invention relates to a MOS semiconductor device and more particularly to a dynamic random access memory (DRAM) having a memory cell composed of a stacked capacitor and an insulated gate MOS transistor.
A memory cell composed of a single MOS transistor and a stacked capacitor has been widely used to realize high integration in memory devices. Moreover, with further increase in the degree of integration of semiconductor devices, it is becoming increasingly difficult to secure the required capacity from the stacked capacitors. Thus, for augmenting the capacity an increase in the surface area of the capacitor electrode is required. However, an attempt to enlarge the surface area leads to an increase in the overall size of the memory cell, which is a completely unacceptable result.
A method for overcoming the above-mentioned drawback provides an increase in the surface area of the capacitor electrode involving an increase in the film thickness of the polycrystalline silicon layer which serves as the lower electrode. This conventional method possesses a significant shortcoming. Specifically, this conventional method of increasing the film thickness of the lower electrode involves the necessity of patterning the thick polycrystalline silicon layer. However, in this process, when polycrystalline silicon remains due to etching residue buried in the narrow portions between the gate electrodes in the underlying layers, short circuiting occurs which adversely affects the operation of the memory cell.
As the simplest way for overcoming such a drawback prolonged etching has been proposed. Such a measure often results in the problem of a reduced electrode area due to side etching of the lower electrode or a breaking of the step edge in the upper electrode, of the capacitor. Moreover, a prolonged etching of the polycrystalline silicon may in turn cause damage to the underlying insulating films which will contribute to the step height on the chip.